A silicon single crystal wafer (which will be also referred to as a silicon wafer hereinafter) which can be a material of a semiconductor device can be generally fabricated by growing a silicon single crystal by a Czochralski method (which will be also referred to as a CZ method hereinafter) and performing a machining process such as cutting or polishing to the obtained silicon single crystal.
In the silicon single crystal grown by the CZ method in this manner, oxidation induced stacking faults called OSFs (Oxidation induced Stacking Faults), which are annularly produced when the silicon single crystal is subjected to a thermal oxidation treatment (for example, 1100° C. for 2 hours), may be generated. It has been revealed that there are also microdefects (which will be referred to as grown-in defects hereinafter) which are formed other than OSFs during crystal growth and adversely affect device performance.
Thus, a method for manufacturing a single crystal to provide a wafer in which these defects are reduced as much as possible has been disclosed in recent years (see, e.g., Patent Literature 1).
FIG. 4 shows a relationship between a pulling rate and a defect generation distribution when V/G is changed and a single crystal is grown where the pulling rate at the time of single-crystal growth using a method disclosed in Patent Literature 1 is V (ram/min) and an average value of a crystalline temperature gradient in a pulling axis direction in a temperature range from a silicon melting point to 1350° C. is G (° C./mm).
It is generally known that a temperature distribution G in a single crystal is dependent on a structure in a CZ furnace (which will be referred to as a hot zone hereinafter) and this distribution hardly varies even if a pulling rate is changed. Thus, in case of the CZ furnaces having the same structure, V/G corresponds to a change in puling rate only. That is, V and V/G have a relationship of a direct proportion. Thus, the pulling rate V is used for a vertical axis in FIG. 4.
In a region where V is relatively high, vacancy type grown-in defects called COPs (Crystal Originated Particles) or FPDs (Flow Pattern Defects), which are provided by agglomerating vacancy type point detects called vacancies (which will be referred to as Va hereinafter), are present in an entire crystal radial region, and this region is called a V-Rich region.
Further, when V is slightly lowered, the OSFs are annularly produced from a periphery of a crystal, and the OSFs shrink toward a center as V is decreased, and eventually the OSFs are annihilated at the crystal center.
When V is further lowered, a neutral (which will be referred to as N hereinafter) region where excess or deficiency of Va or interstitial point defects called interstitial silicon (which will be referred to as I hereinafter) is less is present. It has been revealed that, in this N region, concentration of Va or I is biased, but its concentration is equal to or less than saturated concentration, no defect is present or presence of a defect cannot be recognized by a current defect detecting method. This N region is classified into an Nv region where Va is dominant or an Ni region where I is dominant.
When V is further lowered, I is supersaturated, and defects of L/D (Large Dislocation: an abbreviation of an interstitial dislocation loop, LSEPD, LEPD, or the like) which can be considered as a dislocation loop which is an agglomeration of I are present at low density, and this region is called an I-Rich region.
When the grown-in defects which are present in the V-Rich region, the OSF region and the I-Rich region appear on a wafer surface, they adversely affect device characteristics, for example, they decrease dielectric breakdown strength of an oxide film in a case where an MOS (Metal Oxide Semiconductor) structure of a device is formed, and hence it is desired that such defects are not present in a wafer surface layer.
Meanwhile, oxygen of approximately 7×1017 to 10×1017 atoms/cm3 (a conversion factor provided by Japan Electronics and Information Technology Industries Association: JEITA is used) is usually contained in a silicon wafer in a supersaturated state. Thus, a large amount of grown-in oxide precipitate nuclei is present in the silicon wafer, and supersaturated oxygen in the silicon wafer is precipitated as oxide precipitates or grown-in oxide precipitate nuclei are grown and actualized when a heat treatment is performed in a device process or the like. Such an oxide precipitate is called a BMD (Bulk Micro Defect).
It is known that, when this BMD is present in a bulk other than a device active region, it is effective since it functions as a gettering site to capture a metal impurity mixed during the device process, but it adversely affects the device characteristics such as junction leakage when it is produced on a silicon wafer surface which is the device active region. Thus, in manufacture of the silicon wafer, the BMDs must be formed in a wafer bulk, and a wafer having a denuded zone (which will be also referred to as a DZ layer hereinafter) where the BMDs or the grown-in defects are not present near a wafer surface which is the device active region is demanded.
In response to these demands in recent years, Patent Literature 1 suggests a method for performing an RTA treatment (Rapid Thermal Annealing: rapid heating/rapid cooling heat treatment) to a silicon wafer which is sliced out from a single crystal of an N region where an agglomerate of Va or I is not present and whose entire plane is the N region. It is to be noted that the RTA treatment is also referred to as an RTP treatment (Rapid Thermal Process). This RTA treatment is a heat treatment method characterized in that a temperature of a silicon wafer is rapidly raised from a room temperature at a temperature raising rate, e.g., 50° C./sec in a nitride forming atmosphere of, e.g., N2 or NH3 or in a mixed gas atmosphere of such a gas and a nitride non-forming atmosphere of, e.g., Ar or H2, the silicon wafer is heated and maintained at a temperature of approximately 1200° C. for tens of seconds, and then the temperature of the silicon wafer is rapidly decreased at a temperature falling rate of, e.g., 50° C./sec.
A mechanism of forming the BMD by performing an oxygen precipitation heat treatment after the RTA treatment is described in Patent Literature 1 or Patent Literature 2 in detail.
Here, the BMD formation mechanism will now be briefly described.
First, in the RTA treatment, Va is implanted from a wafer surface while maintaining a high temperature which is, e.g., 1200° C. in an N2 atmosphere, and redistribution and annihilation with I occur due to diffusion of Va during cooling in a temperature range of 1200° C. to 700° C. at a temperature falling rate of, e.g., 5° C./sec. Consequently, Va is non-uniformly distributed in a bulk.
When a wafer in such a state is subjected to a heat treatment at, e.g., 800° C., oxygen is precipitously clustered in a region with high Va concentration, but the oxygen is not clustered in a region with low Va concentration.
In this state, subsequently, a heat treatment is performed at, e.g., 1000° C. for a fixed time, the clustered oxygen grows, and the BMDs are formed. As described above, when the oxygen precipitation heat treatment is performed to the silicon wafer subjected to the RTA treatment, the BMDs having a distribution in a wafer depth direction are formed in accordance with a Va concentration profile formed by the RTA treatment.
Thus, the desired Va concentration profile is formed in the silicon wafer by performing the RTA treatment while controlling conditions such as an atmosphere, a maximum temperature, a retention time, and others, and the oxygen precipitation heat treatment is performed to the thus obtained silicon wafer, thereby manufacturing a silicon wafer having a desired BMD profile in a depth direction.
Further, Patent Literature 3 discloses that an oxide film is formed on a surface when the RTA treatment is performed in an oxygen gas atmosphere, I is implanted from an oxide film interface, and hence BMD formation is suppressed. In this manner, the RTA treatment can promote the BMD formation or, contrarily, can suppress the same depending on conditions such as an atmospheric gas, a maximum retention temperature, and others. Since such an RTA treatment is an annealing performed in a very short time, outward diffusion of the oxygen hardly occurs, and a decrease in oxygen concentration in a surface layer can be ignored.
In case of Patent Literature 1, since no grown-in defect is present in the silicon wafer which can be a material, it seems that no problem occurs even if the RTA treatment is performed. However, when a TDDB (Time Dependent Dielectric Breakdown) characteristic which is an aged breakdown characteristic representing long-term reliability of an oxide film is measured after a silicon wafer whose entire plane consists of an N region is prepared and the RTA treatment is performed, in an Nv region of the silicon wafer, a TZDB (Time Zero Dielectric Breakdown) characteristic which is one of oxide film reliabilities is hardly lowered, but there is a flaw that the TDDB characteristic is lowered.
Furthermore, Patent Literature 4 suggests a method of performing a high-temperature RTA treatment of 1300° C. or more to a silicon wafer whose entire plane consists of an N region. According to this method, a large-sized oxide precipitate which can be a factor of degradation of the TDDB characteristic can be dissolved since the temperature is high, and the excellent TDDB characteristic can be provided. Moreover, it is possible to manufacture a silicon wafer having a BMD profile based on diffusion of Va. However, since a difference in temperature between a pin which supports a wafer in an RTA treatment apparatus and the silicon wafer is considerable, strong stress is produced in a section around the pin, and there is a flaw that slip dislocations are generated.
Additionally, Patent Literature 5 discloses another method for forming a DZ layer in a surface layer. This is a method for applying light pulses from a wafer front surface for approximately one to five seconds to heat the surface to approximately 1000° C., fixing a wafer back surface to a heat sink, maintaining it at a temperature less than 900° C. to decrease a temperature distribution from the wafer front surface toward the back surface, and thereby forming the DZ layer in the vicinity of the front surface. However, according to such a method, since the back surface of the wafer must be brought into contact with the heat sink, there is a problem that a contact portion is apt to be damaged or contaminated and contamination possibly spreads from a member of the heat sink.